In today's highly developed technologies, the production of semiconductor memories is greatly dependent on some particularly important design techniques. One of these particularly important design techniques is the realization of the so-called bit line dummy concept or pseudo bit line concept.
This concept comprises a single or a plurality of dummy bit lines or pseudo bit lines which are used as part of a (temporally) self-synchronizing block in a memory macro. In this case, the purpose of the dummy bit line as part of a synchronization circuit is to provide for the worst case with regard to capacitance, resistance and leakage current with respect to an active genuine bit line during a reading operation (READ operation) and writing operation (WRITE operation). In other words, the dummy bit line is intended to reflect the same properties and dependencies with respect to the production process of the corresponding semiconductor memory and the technology used therefore as the bit lines of the corresponding semiconductor memory.
With the aid of FIG. 1, the functioning of a bit line will now be explained with an example on the basis of an SPSRAM memory cell (“Single Port Static Random Access Memory” memory cell) comprising six transistors. The SPSRAM memory cell comprises two cross-coupled inverters (in this case, each inverter in the memory cell in FIG. 1 comprises an NMOS transistor (bottom) and a PMOS transistor (top), and two access transistors 2 (right and left)). In FIG. 1, the memory cell 1 is connected to the bit line 11 on the left and to the so-called bit line bar 12 on the right. While the bit line 11 has, during writing, the information to be written to the memory cell 1 and, during reading, the information read from the memory cell 1 or the corresponding potential (generally VDD for a logic 1 or a logic HIGH level, and VSS for a logic 0 or a logic LOW level), the bit line bar 12 (apart from the precharge phase described in detail later) has in each case the corresponding complement with respect to the potential or logic level of the bit line 11. In other words, if the bit line 11 has a logic LOW level (HIGH level) after the READ operation or a logic LOW level (HIGH level) during the WRITE operation, the bit line bar 12 has the logic HIGH level (LOW level) at the same time.
It should be noted that the bit line 11 is also called bit line true and the bit line bar 12 is also called bit line complement.
During a writing operation, therefore, the bit line 11 and/or the bit line bar 12 is charged to a potential corresponding to the information to be written to the memory cell 1. By activation of the word line 13, the potential of the bit line 11 or the corresponding logic level is then written to the memory cell 1. To put it more precisely, upon an activation of the word line 13 during a writing operation, the potential of a left-hand internal memory node 3 is set to the potential of the bit line 11. In the case of the memory cell 1 in FIG. 1, the potential of the left-hand internal memory node 3 reproduces the information of the memory cell itself, while a right-hand internal memory node 4 of the memory cell 1 in each case reproduces the complement of the information stored in the memory cell 1. It is possible equally well to activate the word line 14 and thus to set the potential of the right-hand internal memory node 4 to the potential of the bit line bar 12, in this case the inverted logic level (the complement of the logic level that would be written in via the bit line 11) being written to the right-hand internal memory node 4, such that the logic level then arises in the left-hand internal memory node 3 as a result of the construction of the memory cell. In other words, an item of information can be written to the memory cell 1 either via the bit line 11 by means of the left-hand word line 13 or by means of the bit line bar 12 by means of the word line 14.
It is generally preferred to work with a logic LOW level on the bit lines in order to write to the memory cell 1. This means that via the bit line bar 12 by means of the right-hand word line 14, a logic 0 is written to the right-hand internal memory node 4 if a logic 1 is to be written to the memory cell 1. By contrast, if a logic 0 is to be written to the memory cell 1, a logic LOW level is written to the left-hand internal node 3 and thus to the memory cell 1 via the bit line 11 with the aid of the word line 13. It is furthermore possible, during WRITE, to jointly activate the word lines 13, 14 and to apply mutually inverse data or levels to the two complementary bit lines 11, 12.
During a reading operation, the information stored in the memory cell 1 is read out onto the bit line 11 and/or onto the bit line bar 12. For this purpose, during the precharge phase, both the bit line 11 and the bit line bar 12 are precharged to a predetermined potential (generally in each case VDD (logic 1 or logic HIGH level)), the word line(s) 13 and/or 14 being deactivated. By virtue of the word line 13 and/or the word line 14 subsequently being activated, the bit line 11 assumes the potential or the logic level of the left-hand internal memory node 3 and/or the bit line bar 12 assumes the potential or the logic level of the right-hand internal memory node 4.
Since the bit line 11 is charged to a potential during the writing operation or precharged to a potential during the reading operation, for the internal sequence of a semiconductor memory comprising the memory cell 1, it is of crucial importance to determine the instant at which the potential of the internal node 3 of the memory cell 1 to be read can be determined by means of the bit line 11. It should be taken into account here that the bit line 11 and the bit line bar 12 are connected to e.g. 512 memory cells 1 in present-day semiconductor memories. Although, during a reading operation and also during a writing operation, in each case only one of said memory cells 1 is activated (written to or read) by means of the corresponding word line 13 or 14 (the word lines usually run perpendicular to the bit lines, that is to say unlike the illustration in FIG. 1), the memory content of the other non-activated memory cells nevertheless influences the behavior of the bit line 11 and the bit line bar 12.
The following proposals exist for solving this problem.
In a first proposal, the right-hand internal memory node 4 of one or more memory cells 1 connected to the dummy bit line is connected to ground (VSS/GND). On account of the cross-coupling of the inverters of the memory cell 1, this forces the left-hand internal memory node 3 permanently to a logic HIGH level.
This proposal has the disadvantage, however, that design rules for protection against ESD (“Electrostatic Discharge”) or latch-up are thereby contravened. In the case of the memory cell in FIG. 1, the PMOS transistor, top right, is connected to VDD, on the one hand, and to VSS, on the other hand, on account of the short-circuited internal memory node 4.
In a second proposal, the right-hand access transistors 2 of the memory cells 1 are not connected to the dummy bit line bar. It is assumed here that the potential at the internal memory node 3 becomes established at VDD or the logic HIGH level on account of the still connected dummy bit line 11, which represents a large capacitance. This proposal entails the risk, however, that an unknown number of memory cells which are connected to the dummy bit line 11 will assume a logic value different than 1, such that in this case the dummy bit line concept does not represent the worst case. As a matter of fact, in this second proposal it is totally unclear to what extent the respective individual construction of the dummy bit line with the connected memory cells represents the worst case, since the magnitude of the proportion of the memory cells which are connected to the dummy bit line and in which a logic 1 or a logic 0 has become established is unknown for the individual semiconductor memory. Furthermore, the proportion of the memory cells which assume the logic value 0 or 1 is crucially dependent on technological fluctuations, such that ultimately the temporal synchronization during the memory access is also dependent on the technological fluctuations. In other words, the semiconductor memory functions in one case, whereas it fails in the other case since the logic value 1 has not become established in too many of the memory cells.